Making dummy fill smarter
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs. Dummy fill is the term given to the metal shapes (usually...
View ArticleEDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes
At its Open Innovation Platform meeting in San Jose today, TSMC put meat on the bones of its announcement last week of reference design flows for the TSMC 20nm digital and analog, and 3DIC (Guide)...
View ArticleCadence and Imec tape out 3nm interconnect test chip
Cadence Design Systems and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes. The joint...
View ArticleMaking dummy fill smarter
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs. Dummy fill is the term given to the metal shapes (usually...
View ArticleEDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes
At its Open Innovation Platform meeting in San Jose today, TSMC put meat on the bones of its announcement last week of reference design flows for the TSMC 20nm digital and analog, and 3DIC (Guide)...
View ArticleCadence and Imec tape out 3nm interconnect test chip
Cadence Design Systems and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes. The joint...
View ArticleSiemens pushes DRC to the left
Siemens Digital Industries Software has expanded its Calibre lineup for design-rule and manufacturability checks with a version of the engine that makes it easier to perform useful checks early in the...
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